1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to repeater circuits.
2. Description of the Related Art
As integrated circuit (IC) technology advances, the speeds at which IC's operate increases while operating voltages generally decrease. As such, the distances at which signals must propagate on a die become an increasingly important factor to consider in IC design. At longer distances, on-die interconnects between a transmitter and a receiver can develop enough resistance and enough capacitance that the signal transition at the receiver can be adversely affected. For example, excessive propagation delay across a long signal interconnect can affect the transition at the receiver in terms of both timing and voltage levels. For example, a signal that propagates too slowly across an interconnect may in some cases not allow sufficient set-up and hold time for the receiver to properly transition from one logic level to another.
In addition to the distances that signals must travel, another factor that must be considered is the number of loads that must be driven. For example, on-chip memory circuits may include a large number of decoder circuits, each of which may include receivers coupled to common transmitter circuits. Thus, a transmitter coupled to an address signal line may be required to drive a corresponding address signal to a number of different receivers each corresponding to a decoder. If a given address signal lacks sufficient drive strength at the receiver, the decoders may not be able to properly decode the correct memory address.
In some cases, extra circuitry may be implemented in an address (or other multi-signal) path to ensure that signals arrive at their intended destinations with sufficient drive strength and within a specified time. Using the address decoder example again, such circuits may ensure that addresses are properly decoded at a given time. For example, static repeater circuits, including two inverters coupled in series, may be used to provide the necessary drive strength. If a clock is to be factored into the path, a circuit such as a NAND gate coupled in series with an inverter may be utilized, with an address signal and a clock signal being inputs to the former. These circuits may provide the drive strength and necessary timing, although some delay may be added to the signal path.